Since 1994, Siemens Austria has been funding the 'Design
Debugging of VHDL Specification' project, aimed at improving the
hardware design cycle. Hardware (VLSI) designers use dedicated
hardware description language such as VHDL (an internationally
standardized language with similarities to Ada). VHDL programs contain
a concurrent part consisting of processes that communicate in parallel
via signals. The behavior of processes is specified by sequential
statements. VHDL programs are compiled and executed, simulating the
behavior of the designed circuit. The outcome of the simulation is a
waveform trace that records signal changes over time. Waveform traces
are then compared with a specification or another trace. In case of
discrepancies, the VHDL program contains a bug which has to be fixed.
Two tools were developed over the duration of the project, to be
used as an extension of the hardware designer's development
environment, which consists out of a VHDL compiler, simulator and a
waveform trace viewer. The waveform compare tool (WFCOMP) automates
the comparison task and provides several different compare modes. WFCOMP
results can be directly used as inputs for the
debugging tool VHDLDIAG. Because of the program size (up to 10 MB
source code and up to several days of simulation time for large
designs), it was decided to use a very abstract model for debugging which
would be suitable for focusing on fault candidates even for large
programs. The model is based on the dependencies between signals and
variables given by the program structure, a concept similar (but not
identical) to program slicing.
Our group is currently working on improving the diagnosis capability,
although these methods are initially intended to be only used with
small VHDL programs. In particular, we have examined extensions of
models for the description of VHDL programs based on modelling the
correct behavior of
- concurrent signal assignments
- the VHDL sequential part
- the VHDL sequential statements considering semantical differences
between signal and variable assignments together with the temporal
consequences and natural diagnoses ordering criteria.
These models do not handle loops and recursive functions, since these
constructs occur rarely in real-world VHDL designs, especially for
synthesise-able programs, which do not allow their use at all. The
behavior model described in our publications has been implemented and is
currently tested using examples from real-world VHDL design projects.
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